| TC260C | TC260DC | TC260E | TC260DE |
| Standard cell | Embedded Array | ||
| ･0.14um drawn,6-layer-metal CMOS process. ･Over 125k usable gate/mm^2(Standard cell) ･Two type of I/O cell sizes. -Narrow for pad -limited designs ･Short for core limited designs. ･4.20um^2 high-density SRAM cells with 512Kbits/block ･Two types of primitive cell libraries -Embedded Array for fast turnaround time -Standard Cell for highest density ･36ps 2-input NAND gate delay @ 10ps input slew,fanout = 2 plus estimated wire length load (CND2 x 4) ･VDD = 1.5V±10% (Core); 1.5V, 2.5V or 3.3V (I/O) ･Typical 2W power dissipation at 200MHz (36mm^2 die) ･Two technology module options ･Precision 2.5V Analog module for mixed-signal applications ･Performance module for optimizing challenging timing paths ･Comprehensive core and high-performance I/O cell library for SLI implementation ･Timing-Driven Flow (TDF) based on commercial EDA tool sign-off for design flexibility ･Wide range of package options including QFP, TBGA,FCBGA, and EPBGA with pin counts and performance to meet all application needs | |||
| TC260 Embedded DRAM Cores ･2 types of DRAM cores -High-bandwidth, 200MHz regular SDRAM with 2~32Mb, 1~4 banks, and 64~256 bits wide per macrocell ･Fast-Access DRAM with 12ns tRC, 2/4/8Mb 256 bits macrocells ･Over 6.4GB/s macrocell bandwidth at 256bits wide ･Synchronous interface. All signals referenced to positive edge of clock ･Automatic refresh ･Byte Write data control ･Typical 62mm2 die for 32Mb DRAM with 500K gates ･Typical 128mm2 die for 64Mb DRAM with 1.5M gates ･1-transistor cell structure utilizing trench capacitor technology | |||
| Embedded DRAM Benefits ･Flexibility in configuring the DRAM macrocell based on application requirements ･High bandwidth due to wide and fast memory busses ･Faster access time than discrete DRAMs ･Fewer external devices and reduction of total and ASIC pin count ･Lower power dissipation?systems with fast and wide memory busses will dissipate significantly less power due to lower-capacitance on-chip connections ･Lower switching noise on data bus between memory and logic | |||
